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| SSM9620M P-CHANNEL ENHANCEMENT-MODE POWER MOSFET Low on-resistance Capable of 2.5V drive Fast switching Simple drive requirement D D D D BVDSS R DS(ON) G -20V 20m -9.5A ID SO-8 S S S Description Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. D G S The SSM9620M is supplied in the SO-8 package, which is widely preferred for commercial and industrial surface-mount applications. This device is well suited for low voltage applications such as DC/DC converters. Absolute Maximum Ratings Symbol VDS VGS ID @ TA=25C ID @ TA=70C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current 1,2 3 3 Rating - 20 12 -9.5 -7.6 -76 2.5 0.02 -55 to 150 -55 to 150 Units V V A A A W W/C C C Continuous Drain Current Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-amb Parameter Thermal Resistance Junction-ambient Max. Value 50 Unit C/W Rev.2.02 3/06/2004 www.SiliconStandard.com 1 of 6 SSM9620M Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol BVDSS BV DSS/ T j Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=-250uA Min. Typ. Max. Units -20 -0.037 20 35 -1 -1 -25 100 - V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25C, ID=-1mA RDS(ON) Static Drain-Source On-Resistance VGS=-4.5V, ID=-9.5A VGS=-2.5V, ID=-6.0A 28 30 6 3.5 26 500 70 300 2158 845 230 VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o VDS=VGS, ID=-250uA VDS=-10V, ID=-9.5A VDS=-20V, VGS=0V VDS=-16V, VGS=0V VGS= 12V ID=-9.5A VDS=-10V VGS=-5V VDS=-10V ID=-9.5A RG=6 ,VGS=-4.5V RD=1.05 VGS=0V VDS=-15V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 Source-Drain Diode Symbol IS ISM VSD Parameter Continuous Source Current ( Body Diode ) Test Conditions VD=VG=0V , VS=-1.2V 1 Min. Typ. Max. Units -2.5 -76 -1.2 A A V Pulsed Source Current ( Body Diode ) Forward On Voltage 2 Tj=25C, IS=-2.5A, VGS=0V Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on FR4 board, t<10 sec. Rev.2.02 3/06/2004 www.SiliconStandard.com 2 of 6 SSM9620M 120 100 T C =25 o C 90 -10V -8.0V 80 T C =150 o C -10V -8.0V -ID , Drain Current (A) -ID , Drain Current (A) 60 -6.0V 60 -6.0V V GS =-4.0V 40 V GS =-4.0V 30 20 0 0 2 4 6 0 0 2 4 6 8 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 40 1.6 35 I D =-9.5A T C =25 I D =-9.5A V GS =4.5V 1.4 Normalized R DS(ON) RDS(ON) (m ) 30 1.2 25 1.0 20 0.8 15 1 2 3 4 5 6 0.6 -50 0 50 100 150 -V GS (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature Rev.2.02 3/06/2004 www.SiliconStandard.com 3 of 6 SSM9620M 10 3 2.5 8 -ID , Drain Current (A) 2 6 PD (W) 4 2 0 25 50 75 100 125 150 1.5 1 0.5 0 0 30 60 90 120 150 T c , Case Temperature ( o C) T c , Case Temperature ( C) o Fig 5. Maximum Drain Current vs. Case Temperature Fig 6. Typical Power Dissipation 1000.00 1 Duty Factor = 0.5 100.00 Normalized Thermal Response (R thja) 100us 1ms 10.00 0.2 0.1 0.1 0.05 -ID (A) 10ms 1.00 100ms 0.02 0.01 PDM Single Pulse 0.01 t T 0.10 1s T c =25 o C Single Pulse Duty Factor = t/T Peak Tj = P DM x Rthja + Ta 0.01 0.1 1 10 100 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 -V DS (V) t , Pulse Width (s) Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance Rev.2.02 3/06/2004 www.SiliconStandard.com 4 of 6 SSM9620M f=1.0MHz 7 10000 6 I D =-9.5A V DS =-10V -VGS , Gate to Source Voltage (V) 5 4 C (pF) Ciss 1000 3 Coss 2 Crss 1 0 0 5 10 15 20 25 30 35 40 100 1 8 15 22 29 Q G , Total Gate Charge (nC) -V DS (V) Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics 100.00 1.2 10.00 0.9 -IS(A) T j =150 o C 1.00 T j =25 o C -VGS(th) (V) 1.3 0.6 0.10 0.3 0.01 0.1 0.4 0.7 1 0 -50 0 50 100 150 -V SD (V) T j , Junction Temperature ( o C) Fig 11. Forward Characteristic of Reverse Diode Fig 12. Gate Threshold Voltage vs. Junction Temperature Rev.2.02 3/06/2004 www.SiliconStandard.com 5 of 6 SSM9620M VDS RD 90% D VDS TO THE OSCILLOSCOPE 0.5 x RATED VDS RG G 10% S -5V VGS VGS td(on) tr td(off) tf Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform VG VDS TO THE OSCILLOSCOPE 0.5 x RATED VDS G S -1~-3mA I G QG -4.5V QGS QGD D VGS I D Charge Q Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. Rev.2.02 3/06/2004 www.SiliconStandard.com 6 of 6 |
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